Zvonko Vranesic
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Zvonko Vranesic [1] Zvonko George Vranesic,
a Croatian Canadian chess and correspondence chess international master [2] , electrical engineer, and professor emeritus at Depature of Electrical and Computer Engineering, Computer Engineering Research Group, University of Toronto. His research interests covers Multiple-Valued Logic Systems, parallel computing along with NUMA, and FPGA. Along with Stephen Brown [3], he co-authored Fundamentals of Digital Logic with VHDL and Verilog Design.
Chess Player
Zvonko Vranesic represented Canada at five Chess Olympiads [6] , he scored a Grandmaster norm at the 19th Chess Olympiad in Siegen [7]. Notable are his wins against Leonid Stein at the 16th Olympiad in Tel Aviv 1964 [8], and versus David Levy in Lone Pine 1975 [9] .
Selected Games
Leonid Stein
David Levy
Selected Publications
1970 …
- Zvonko Vranesic, E. Stewart Lee, Kenneth C. Smith (1970). A Many-Valued Algebra for Switching Systems. IEEE Transactions on Computers, Vol. 19, No. 10
- Zvonko Vranesic, Kenneth C. Smith (1974). Engineering aspects of multi-valued logic systems. IEEE Transactions on Computers, Vol. 7, No. 9
- Michael Valenti, Zvonko Vranesic (1977). Experiences with CHUTE. ACM conference
- Zvonko Vranesic (1977). Multiple-Valued Logic: An Introduction and Overview. IEEE Transactions on Computers, Vol. 26, No. 12
- Carl Hamacher, Zvonko Vranesic, Safwat Zaky (1978). Computer Organization. McGraw-Hill
1980 …
- Hussein T. Mouftah, Kenneth C. Smith, Zvonko Vranesic (1980). Ternary Rate-Multipliers. IEEE Transactions on Computers, Vol. 29, No. 10
- Jonathan Rose, Wayne M. Loucks, Zvonko Vranesic (1985). FERMTOR: A Tunable Multiprocessor Architecture. IEEE Micro, Vol. 5, No. 4
- Jonathan Rose, W. Martin Snelgrove, Zvonko Vranesic (1988). Parallel standard cell placement algorithms with quality equivalent to simulated annealing. IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. 7, No. 3
1990 …
- Zeljko Zilic, Zvonko Vranesic (1993). Current-Mode CMOS Galois Field Circuits. ISMVL 1993
- Zeljko Zilic, Zvonko Vranesic (1995). A Multiple-Valued Reed-Muller Transform for Incompletely Specified Functions. IEEE Transactions on Computers, Vol. 44, No. 8 [11]
- Zeljko Zilic, Zvonko Vranesic (1996). Using BDDs to Design ULMs for FPGAs. FPGA 1996
- Zvonko Vranesic (1998). The FPGA Challenge. ISMVL 1998
- Ante Grbić, Stephen Brown, Steve Caranci, Robin Grindley, Mitchell Gusat, Guy Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko Vranesic, Zeljko Zilic (1998). Design and Implementation of the NUMAchine Multiprocessor. DAC 1998, pdf [12]
- Stephen Brown, Zvonko Vranesic (1999). Fundamentals of Digital Logic with VHDL Design. McGraw-Hill
2000 …
- Robin Grindley, Tarek Abdelrahman, Stephen Brown, Steve Caranci, D. DeVries, Benjamin Gamsa, Ante Grbić, Mitchell Gusat, R. Ho, Orran Krieger, Guy Lemieux, K. Loveless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko Vranesic, Zeljko Zilic (2000). The NUMAchine Multiprocessor. ICPP 2000, pdf
- Valavan Manohararajah, Terry P. Borer, Stephen Brown, Zvonko Vranesic (2002). Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices. FPL 2002
- Stephen Brown, Zvonko Vranesic (2003). Fundamentals of Digital Logic with Verilog Design. McGraw-Hill
- Valavan Manohararajah, Stephen Brown, Zvonko Vranesic (2006). Adaptive FPGAs: High-Level Architecture and a Synthesis Method. FPL 2006, pdf
- Valavan Manohararajah, Stephen Brown, Zvonko Vranesic (2006). Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping. IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. 25, No. 11
- Stephen Brown, Zvonko Vranesic (2007). Fundamentals of Digital Logic with Verilog Design. McGraw-Hill, 2nd edition, amazon
- Stephen Brown, Zvonko Vranesic (2008). Fundamentals of Digital Logic with VHDL Design. McGraw-Hill, 3rd edition, amazon
2010 …
- Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Naraig Manjikian (2011). Computer Organization and Embedded Systems. 6th edition, McGraw-Hill, amazon
- Franjo Plavec, Zvonko Vranesic, Stephen Brown (2013). Exploiting Task- and Data-Level Parallelism in Streaming Applications Implemented in FPGAs. TRETS, Vol. 6, No. 4
External Links
- Zvonko Vranesic from Wikipedia
- Z.G. Vranesic homepage
- Vranesic Zvonko | The Chess Federation of Canada - La Fédération Canadienne des Échecs
- The chess games of Dr. Zvonko Vranesic from chessgames.com
- Zvonko Vranesic Croatian-Canadian International Chess Master and Professor at the University of Toronto by Nenad N. Bach and Darko Žubrinić, CROWN - Croatian World Network, July 09, 2016
- Vranesic, Zvonko FIDE Chess Profile
References
- ↑ Zvonko Vranesic Croatian-Canadian International Chess Master and Professor at the University of Toronto
- ↑ Biography - Z.G. Vranesic
- ↑ Professor Stephen Brown - University of Toronto
- ↑ Michael Valenti (1974). CHUTE I, An Easily Modifiable Chess Playing Program. M.A.Sc. thesis, Depature of Electrical Engineering, University of Toronto
- ↑ Michael Valenti, Zvonko Vranesic (1977). Experiences with CHUTE. Proceedings of the ACM conference
- ↑ Zvonko Vranesic - Olympiads
- ↑ Zvonko Vranesic from Wikipedia
- ↑ Dr. Zvonko Vranesic vs Leonid Stein from chessgames.com
- ↑ David Neil Lawrence Levy vs Dr. Zvonko Vranesic from chessgames.com
- ↑ dblp: Zvonko G. Vranesic
- ↑ Reed–Muller code from Wikipedia
- ↑ Documentation on the NUMAchine Multiprocessor