TBM
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TBM (Trailing Bit Manipulation Instructions),
an x86-64 expansion of bit-manipulation instructions, introduced by AMD with the Bulldozer microarchitecture, which also comprises the AVX, BMI1 and XOP instruction sets. TBM requires bit 21 set in ECX of CPUID EAX=80000001H [1]. More recent AMD Jaguar and Zen based processors do not support TBM [2].
Least Significant One Bit
BLSFILL
Fill From Lowest Set Bit. Union with the decrement.
BLSFILL reg64, reg/mem64
dest ::= src | (src - 1);
src | (src - 1) = dest
0x0040201008040200 0x00402010080401FF 0x00402010080403FF
. . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 1 . . . . . . . 1 . . . . . . . 1 .
. . . . . 1 . . . . . . . 1 . . . . . . . 1 . .
. . . . 1 . . . . . . . 1 . . . . . . . 1 . . .
. . . 1 . . . . | . . . 1 . . . . = . . . 1 . . . .
. . 1 . . . . . . . 1 . . . . . . . 1 . . . . .
. 1 . . . . . . 1 . . . . . . . 1 1 . . . . . .
. . . . . . . . 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1BLSIC
Isolate Lowest Set Bit and Complement. Union of complement and decrement.
BLSIC reg64, reg/mem64
dest ::= ~src | (src - 1);
src -> ~src | (src - 1) = dest
0x0040201008040200 0x00402010080401FF 0x00402010080403FF 0xFFFFFFFFFFFFFDFF
. . . . . . . . 1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 1 1 1 1 1
. . . . . . 1 . 1 1 1 1 1 1 . 1 . . . . . . 1 . 1 1 1 1 1 1 1 1
. . . . . 1 . . 1 1 1 1 1 . 1 1 . . . . . 1 . . 1 1 1 1 1 1 1 1
. . . . 1 . . . 1 1 1 1 . 1 1 1 . . . . 1 . . . 1 1 1 1 1 1 1 1
. . . 1 . . . . -> 1 1 1 . 1 1 1 1 | . . . 1 . . . . = 1 1 1 1 1 1 1 1
. . 1 . . . . . 1 1 . 1 1 1 1 1 . . 1 . . . . . 1 1 1 1 1 1 1 1
. 1 . . . . . . 1 . 1 1 1 1 1 1 1 . . . . . . . 1 . 1 1 1 1 1 1
. . . . . . . . 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1TZMSK
Mask From Trailing Zeros. Intersection of complement and decrement sets all bits below the least significant one bit, and clears all other bits, including the LS1B itself.
dest ::= ~src & (src - 1);
src -> ~src & (src - 1) = dest
0x0040201008040200 0x00402010080401FF 0x00402010080403FF 0x00000000000001FF
. . . . . . . . 1 1 1 1 1 1 1 1 . . . . . . . . . . . . . . . .
. . . . . . 1 . 1 1 1 1 1 1 . 1 . . . . . . 1 . . . . . . . . .
. . . . . 1 . . 1 1 1 1 1 . 1 1 . . . . . 1 . . . . . . . . . .
. . . . 1 . . . 1 1 1 1 . 1 1 1 . . . . 1 . . . . . . . . . . .
. . . 1 . . . . -> 1 1 1 . 1 1 1 1 & . . . 1 . . . . = . . . . . . . .
. . 1 . . . . . 1 1 . 1 1 1 1 1 . . 1 . . . . . . . . . . . . .
. 1 . . . . . . 1 . 1 1 1 1 1 1 1 . . . . . . . 1 . . . . . . .
. . . . . . . . 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1Least Significant Zero Bit
BLCFILL
Fill From Lowest Clear Bit. Intersection with the increment.
BLCFILL reg64, reg/mem64
dest ::= src & (src + 1);
src & (src + 1) = dest
0x80C0E0F0F8FCFEFF 0x80C0E0F0F8FCFF00 0x80C0E0F0F8FCFE00
. . . . . . . 1 . . . . . . . 1 . . . . . . . 1
. . . . . . 1 1 . . . . . . 1 1 . . . . . . 1 1
. . . . . 1 1 1 . . . . . 1 1 1 . . . . . 1 1 1
. . . . 1 1 1 1 . . . . 1 1 1 1 . . . . 1 1 1 1
. . . 1 1 1 1 1 & . . . 1 1 1 1 1 = . . . 1 1 1 1 1
. . 1 1 1 1 1 1 . . 1 1 1 1 1 1 . . 1 1 1 1 1 1
. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 . . . . . . . . . . . . . . . .
BLCI
Isolate Lowest Clear Bit. Union with the complement of the increment.
BLCI reg64, reg/mem64
dest ::= src | ~(src + 1);
src | ~(src + 1) = dest
0x80C0E0F0F8FCFEFF 0x7F3F1F0F070300FF 0xFFFFFFFFFFFFFEFF
. . . . . . . 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
. . . . . . 1 1 1 1 1 1 1 1 . . 1 1 1 1 1 1 1 1
. . . . . 1 1 1 1 1 1 1 1 . . . 1 1 1 1 1 1 1 1
. . . . 1 1 1 1 1 1 1 1 . . . . 1 1 1 1 1 1 1 1
. . . 1 1 1 1 1 | 1 1 1 . . . . . = 1 1 1 1 1 1 1 1
. . 1 1 1 1 1 1 1 1 . . . . . . 1 1 1 1 1 1 1 1
. 1 1 1 1 1 1 1 . . . . . . . . . 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
BLCIC
Isolate Lowest Clear Bit and Complement. Intersection of the complement with the increment.
BLCIC reg64, reg/mem64
dest ::= ~src & (src + 1);
src -> ~src & (src + 1) = dest
0x80C0E0F0F8FCFEFF 0x7F3F1F0F07030100 0x80C0E0F0F8FCFF00 0x0000000000000100
. . . . . . . 1 1 1 1 1 1 1 1 . . . . . . . . 1 . . . . . . . .
. . . . . . 1 1 1 1 1 1 1 1 . . . . . . . . 1 1 . . . . . . . .
. . . . . 1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 . . . . . . . .
. . . . 1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 1 . . . . . . . .
. . . 1 1 1 1 1 -> 1 1 1 . . . . . & . . . 1 1 1 1 1 = . . . . . . . .
. . 1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 1 1 1 . . . . . . . .
. 1 1 1 1 1 1 1 1 . . . . . . . 1 1 1 1 1 1 1 1 1 . . . . . . .
1 1 1 1 1 1 1 1 . . . . . . . . . . . . . . . . . . . . . . . .
BLCMSK
Mask From Lowest Clear Bit. Exclusive or with the increment.
BLCMSK reg64, reg/mem64
dest ::= src ^ (src + 1);
src ^ (src + 1) = dest
0x80C0E0F0F8FCFEFF 0x80C0E0F0F8FCFF00 0x00000000000001FF
. . . . . . . 1 . . . . . . . 1 . . . . . . . .
. . . . . . 1 1 . . . . . . 1 1 . . . . . . . .
. . . . . 1 1 1 . . . . . 1 1 1 . . . . . . . .
. . . . 1 1 1 1 . . . . 1 1 1 1 . . . . . . . .
. . . 1 1 1 1 1 ^ . . . 1 1 1 1 1 = . . . . . . . .
. . 1 1 1 1 1 1 . . 1 1 1 1 1 1 . . . . . . . .
. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 . . . . . . .
1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 1 1 1 1 1
BLCS
Set Lowest Clear Bit. Union with the increment.
BLCS reg64, reg/mem64
dest ::= src | (src + 1);
src | (src + 1) = dest
0x80C0E0F0F8FCFEFF 0x80C0E0F0F8FCFF00 0x80C0E0F0F8FCFFFF
. . . . . . . 1 . . . . . . . 1 . . . . . . . 1
. . . . . . 1 1 . . . . . . 1 1 . . . . . . 1 1
. . . . . 1 1 1 . . . . . 1 1 1 . . . . . 1 1 1
. . . . 1 1 1 1 . . . . 1 1 1 1 . . . . 1 1 1 1
. . . 1 1 1 1 1 | . . . 1 1 1 1 1 = . . . 1 1 1 1 1
. . 1 1 1 1 1 1 . . 1 1 1 1 1 1 . . 1 1 1 1 1 1
. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 1 1 1 1 1
T1MSKC
Inverse Mask From Trailing Ones. Union of complement and increment.
T1MSKC reg64, reg/mem64
dest ::= ~src | (src + 1);
src -> ~src | (src + 1) = dest
0x80C0E0F0F8FCFEFF 0x7F3F1F0F07030100 0x80C0E0F0F8FCFF00 0xFFFFFFFFFFFFFF00
. . . . . . . 1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 1 1 1 1 1 1
. . . . . . 1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 1 1 1 1 1 1 1
. . . . . 1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 1 1 1 1 1 1 1 1
. . . . 1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 1 1 1 1 1 1 1 1 1
. . . 1 1 1 1 1 -> 1 1 1 . . . . . | . . . 1 1 1 1 1 = 1 1 1 1 1 1 1 1
. . 1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 1 1 1 1 1 1 1 1 1 1 1
. 1 1 1 1 1 1 1 1 . . . . . . . 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 . . . . . . . . . . . . . . . . . . . . . . . .
Misc
BEXTR
An immediate form of the variable BMI1 Bit Field Extract.
BEXTR reg32, reg/mem32, imm32
BEXTR reg64, reg/mem64, imm32See also
Obtaining and Clearing the Least Significant Bit (LS1B)
Manuals
- AMD64 Architecture Programmer’s Manual Volume 3: General-Purpose and System Instructions (pdf) [3]
- Software Optimization Guide for AMD Family 15h Processors (pdf) 9.8 Optimizing with BMI and TBM Instructions, pp. 163
External Links
References
- ↑ AMD CPUID Specification (pdf)
- ↑ Family 16h Models 00h-0Fh AMD A-Series Mobile Accelerated Processor Product Data Sheet (pdf)
- ↑ Moved BMI and TBM instructions from Volume 4 to Volume 3 in September 2011