Marc BoulC3A9

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Marc Boulé [1] Marc Boulé,

a Canadian electrical engineer and senior lecturer (Maître d’enseignement) at École de technologie supérieure. He holds a Ph.D. on hardware verification in 2008 and a M.Sc. on the topic of FPGA move generation for the game of chess in 2003 - both degrees were defended at McGill University under advisor Zeljko Zilic. The FPGA move was incorporated in his chess program MBChess [2].

Marc Boulé (2002). An FPGA Move Generator for the Game of Chess. Masters thesis, McGill University, Montréal, advisor: Zeljko Zilic, co-supervisor: Monty Newborn
Marc Boulé, Zeljko Zilic (2002). An FPGA Move Generator for the Game of Chess. McGill University
Marc Boulé, Zeljko Zilic (2002). An FPGA Move Generator for the Game of Chess. ICGA Journal, Vol. 25, No. 2
Marc Boulé, Zeljko Zilic (2003). FPGA Hardware Acceleration: From Chess Playing to Automated Theorem Proving. poster presentation, Micronet 2003, Toronto, Sept. 2003.
Marc Boulé (2008). Assertion-Checker Synthesis for Hardware Verification, In-Circuit Debugging and On-Line Monitoring. Ph.D. thesis, McGill University, advisor: Zeljko Zilic

Jason G. Tong, Marc Boulé, Zeljko Zilic (2010). Defining and Providing Coverage for Assertion-Based Dynamic Verification. Journal of Electronic Testing, Vol. 26
Jason G. Tong, Marc Boulé, Zeljko Zilic (2016). Accelerating assertion assessment using GPUs. HLDVT 2016